Pre-Conference Tutorials and Workshops

RT2014 will offer in-depth a tutorial and two short courses Sunday before the conference. These sessions are offered at an additional fee, as shown on the Registration page. Choose from among them when you register for RT2014. Since the tutorial and the short courses are in parallel, one should choose either the tutorial or the short courses. Both sessions are one day program.


ATCA and μTCA for Physics Experiments
Organizer: Kay Rehlich, DESY
This is a one day tutorial, all day Sunday May 25.

We are pleased to invite you to the 7th ATCA /MicroTCA for Physics. The Tutorial is organized under the auspices of IEEE and the Laboratory Members of the PICMG xTCA for Physics open standards consortium.



Short courses

Registering “short course”, one can attend two courses. Both are half day courses and given on Sunday morning and afternoon.

I. Using HTML5 in Web Applications as clients for slow control

Lecturer: Hans Meulen, Stockholm University
The details will be shown soon.

II. Timing issues and algorithm implementation for FPGA based designs

Lecturer: Wojciech Jalmuzna


Modern FPGA based designs use fast communication protocols and interface with peripherals, which provide data with Gbps speeds. Very often it is necessary to use multiple clock domains in the same design. This implies a lot of constraints on the FPGA layout and force developers to control implementation process on high level of detail. The course shows possible tools and procedures to accomplish this task and give introduction to algorithm implementation, which allows to use fast computation resources in an optimal way.

Part I: Understanding timing constraints

The part gives short introduction to FPGA design timing constraints and covers more advanced issues such as clock domain crossing and dealing with metastability for asynchronous input signals.

Part II: Advanced methods of algorithm implementation

The part compares different approaches to algorithm implementation and gives short introduction to High Level Synthesis tools.

Program (Preliminary)

9:00-9:30 Registration
9:30-12:30 Short course-I (HTML5)
12:20-13:30 Lunch
13:30-16:30 Short course-II (FPGA)


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